This invention relates to a synchronous semiconductor integrated circuit which generates an internal clock signal synchronizing with an external clock signal and performs input/output control of data in synchronization with the internal clock signal, and more particularly to a synchronous semiconductor integrated circuit used in, for example, a synchronous DRAM or a RAMBUS DRAM which generates an internal clock according to the load characteristic of an external data bus onto which data is outputted.
As the operating speed of a semiconductor integrated circuit is made higher, this gives rise to a problem: even a slight delay between the internal clock signal driving the internal circuit and the external clock signal causes the circuit to operate erroneously.
Such a problem can be solved by incorporating a clocked delay control circuit into a semiconductor integrated circuit.
The clocked delay control circuit synchronizes with an external clock signal and generates a delay signal delayed for n (n is an integer) periods of the external clock signal. This signal is used as an internal clock signal.
Hereinafter, the clocked delay control circuit will be explained briefly.
Clocked delay control circuits are available in two types: those of the SAD type using a synchronous adjustable delay (hereinafter, referred to as SAD) and those of the DLL type using a delay locked loop (hereinafter, referred to as DLL). Clocked delay control circuits of both types use delay lines to synchronize the internal clock signal with the external clock signal.
The SAD type of clocked delay control circuit generates a signal caused to lag behind the external clock signal by an integral multiple of the period without using a feedback loop and uses this signal as an internal clock signal. The PLL type of clocked delay control circuit compares the phase of the internal clock signal with that of the external clock signal using a feedback loop and controls the delay lines according to the phase difference, thereby generating an internal clock signal synchronizing with the external clock.
FIG. 1 is a block diagram of a conventional clocked delay control circuit of the SAD type. The clocked delay control circuit includes of a clock receiver 11 to which an external clock signal ExtCLK is inputted, a delay monitor 12 for delaying the output of the clock receiver 11, a forward pulse delay line 14 which is composed of unit delay circuits 13 and delays the output signal FCL of the delay monitor 12 by causing the unit delay circuits 13 to propagate the output signal FCL as a forward pulse in sequence, a control circuit 15 to which the output signal CLK of the clock receiver 11 is supplied, a backward pulse delay line 16 which is composed of unit delay circuits 13 and delays the backward pulse transferred from the forward pulse delay line 14 by causing the unit delay circuits 13 to propagate the backward pulse sequentially, and an output buffer 17 to which the output signal RCL from the backward pulse delay line 16 is inputted and outputs an internal clock signal IntCLK.
The operating principle of the clocked delay control circuit will be explained by reference to timing charts in FIGS. 2A to 2E.
As shown in FIGS. 2A to 2E, the external clock signal ExtCLK with a period of T is amplified and waveform-shaped by the clock receiver 11 and becomes a signal CLK delayed for a delay time of tRC in the clock receiver 11. The signal CLK is inputted to the control circuit 15 and simultaneously to the delay monitor 12. The delay monitor 12 has a delay time of tDM (tDM=tRC+tDR) equal to the sum of the delay time tRC in the clock receiver 11 and the delay time tDR in the output buffer 17. The signal delayed by the delay monitor 12 is inputted as a signal FCL to the forward pulse delay line 14.
The control circuit 15 has the function of, when the signal CLK is at the high level, stopping the propagation of the forward pulse on the forward pulse delay line 14 and transferring the signal to the backward pulse delay line 16. Thus, the signal FCL is propagated and delayed as a forward pulse over the forward pulse delay line 14 during a period of (T-tDM) until the signal CLK has risen. Thereafter, the signal FCL is transferred to the backward pulse delay line 16 (this time is represented by t in FIGS. 2A to 2E).
The signal transferred to the backward pulse delay line 16 is propagated and delayed as a backward pulse over as many unit delay circuits 13 in the backward pulse delay line 16 as the forward pulse has in the forward pulse delay line 14. Then, the backward pulse delay line 16 outputs the signal as a signal RCL delayed a period of (T-tDM) from time t. The signal RCL is further delayed for the delay time tDR at the output buffer 17 and outputted as an internal clock signal IntCLK.
A delay time of .DELTA.TOTAL on the internal clock signal IntCLK with respect to the external clock signal ExtCLK is given as follows: EQU .DELTA.TOTAL=tRC+tDM+2(T-tDM)+tDR (1)
Since tRC+tDR=tDM, equation (1) is simplified as follows: ##EQU1##
Thus, the internal clock signal starts to synchronize with the external clock signal at the third period of the external clock signal.
FIG. 3 is a block diagram of a conventional clocked delay control circuit of the DLL type.
The DLL clocked delay control circuit includes a clock receiver 11, a delay line 14A, an output buffer 17, a control circuit 15A composed of a shift register, a delay monitor 12A, and a phase comparator 18.
The operating principle of the DLL clocked delay control circuit will be explained by reference to timing charts in FIGS. 4A to 4E.
As shown in FIGS. 4A to 4E, the external clock signal ExtCLK with a period of T is amplified and waveform-shaped by the clock receiver 11. The resulting signal is then outputted as a signal CLKA delayed for the delay time tRC in the clock receiver 11. The signal CLKA is inputted to the delay line 14A and phase comparator 18.
As shown in FIG. 3, the delay line 14A is composed of n unit delay circuits 13 connected in a multistage manner. The signal CLKA is inputted to the unit delay circuit 13k at the k-th stage (1.ltoreq.k.ltoreq.n). Then, the unit delay circuit 13n at the n-th stage, the last stage, outputs the signal as a signal CLKAd.
The signal CLKAd is inputted to the delay monitor 12A. The delay monitor 12A has a delay time of tDM (tDM=tRC+tDR) equal to the sum of the delay time tRC in the clock receiver 11 and the delay time tDR in the output buffer 17. The signal delayed by the delay monitor 12A is inputted as a signal CLKB to the phase comparator 18, which compares the phase of the signal CLKB with that of the previous signal CLKA. The result of the comparison is inputted to the control circuit 15A. According to the result of the comparison, the control circuit 15A changes the position of the stage of the unit delay circuit 13 to which the signal CLKA is inputted.
The signal CLKAd is further delayed by the output buffer 17 for its delay time tDR. The delayed signal is outputted as an internal clock signal IntCLK.
If the delay time occurring on the delay line 14A with respect to the signal CLKA is t(k), a delay time of .DELTA.TOTAL on the internal clock signal IntCLK with respect to the external clock signal ExtCLK is given by the following equation: EQU .DELTA.TOTAL=tRC+t(k)+tDR (3)
The phase difference .DELTA.AB between signal CLKA and signal CLKB is: EQU .DELTA.AB=t(k)+tDM (4)
When k is so determined that the phase of signal CLKA is equal to that of signal CLKB (.DELTA.AB=T), it follows from equations (3) and (4) and the equation tDM=tRC+tDR that the delay time of the internal clock signal IntCLK from the external clock signal ExtCLK is T. This means that the internal clock signal IntCLK synchronizes with the external clock signal ExtCLK.
In the circuit of FIG. 3, the principle of putting signal CLKA in phase with signal CLKB will be explained. It is assumed that signal CLKA is inputted to the unit delay circuit 13k at the k-th stage of the delay line 14A and signal CLKB lags in phase behind signal CLKA. At this time, to shorten the length of the delay line along which signal CLKA propagates (or decrease the number of unit delay circuits), that is, to make the value of k larger to make t(k) smaller, a right shift signal is supplied from the phase comparator 18 to the control circuit 15A. Conversely, when signal CLKB leads signal CLKA in phase, a left shift signal is supplied from the phase comparator 18 to the control circuit 15A to lengthen the delay line along which signal CLKA propagates. Repeating such processes enables signal CLKA to be put in phase with signal CLKB.
While in the circuit of FIG. 3, the delay line 14A and control circuit 15A are composed of such digital circuits as logic circuits and shift registers, they may be constructed by using an analog circuit as shown in FIG. 5 to improve the accuracy of clock synchronization.
A conventional clocked delay control circuit shown in FIG. 5 uses a voltage controlled delay line (hereinafter, referred to as VCD) 14B as the delay line and a charge pump circuit 19 and a loop filter circuit 15B in place of the previous control circuit 15A.
Since the operating principle of the circuit is the same as that of the DLL clocked delay control circuit with a digital circuit configuration of FIG. 3, a detailed explanation of it will not be given and only what differs from FIG. 3 will be described.
A delay line VCD 14B is composed of unit delay elements. Unlike the circuit of FIG. 3 where the number of unit delay elements in the delay line over which signal CLKA propagates is changed according to the output of the control circuit 15A, the circuit of FIG. 5 is such that the delay time per stage of unit delay element is varied according to the output of the loop filter circuit 15B, thereby adjusting the propagation delay time tVCDL on the entire delay line 14B, which synchronizes the internal clock signal IntCLK with the external clock signal ExtCLK.
The charge pump circuit 19 used has the function of generating an analog voltage corresponding to the output signal of the phase comparator 18. The loop filter circuit 15B has the function of enabling a stable operation without the oscillation of the analog feedback loop.
As described above, any type of clocked delay control circuit uses a delay monitor. To increase the accuracy of the synchronization of the internal clock signal with the external clock signal, the delay time tDM in the delay monitor has to be made exactly equal to the sum of the delay time tRC in the receiver and the delay time tDR in the output buffer. Namely, the accuracy of the delay monitor has a large effect on the final accuracy of the synchronization of the clocked delay control circuit.
FIG. 6 is a block diagram of an internal clock signal generator circuit using a conventional SAD clocked delay control circuit and a data input/output circuit that inputs and outputs data in synchronization with the internal clock signal generated at the internal clock signal generator circuit.
The internal clock signal generator circuit 10 includes a clock receiver 11, a synchronous delay control circuit 15C composed of, for example, the forward pulse delay line 14, control circuit 15, and backward pulse delay line 16 of FIG. 1, a clock driver 16A, an output control circuit 16B, and a delay monitor 12B. The data input/output circuit 20 includes a data input/output amplifier 21, an output buffer 22, an output driver 23, and a data receiver 24.
Numeral 30 indicates an equivalent circuit equivalently representing a controller and an external terminal system connected to an external data bus. The equivalent circuit 30 is composed of a terminal resistance 31 and a load capacitance 32.
With such a configuration, the delay monitor 12B is designed to have a delay almost equal to the sum of the input delay time and output delay time in the internal clock signal generator circuit 10. Specifically, the delay monitor 12B is composed of, for example, multiple stages of inverters 35 connected in series as shown in FIG. 7. The output signal CLK from the clock receiver 11 is inputted to the first stage of the inverters 35 connected in series. The output signal of the inverter 35 at the last stage is inputted as signal FCL to the synchronous delay control circuit 15C.
The delay monitor 12B of FIG. 7 further includes auxiliary inverters 36. Fine adjustment of the delay can be made by connecting the auxiliary inverters 36 in parallel with the inverters 35. To make the auxiliary inverters 36 enable, the parts previously grounded are disconnected from the ground.
The sum of the input delay time and output delay time in the clocked delay control circuit is not always constant and varies greatly, depending on the processing condition in the manufacture, the temperature in the environment where the device is used, the supply voltage used, the load conditions for the external data bus (including the terminal resistance 31 and load capacitance 32) and the like.
As a result, even with the conventional delay adjusting method using the inverter chain as shown in FIG. 7, the delay required by the delay monitor 12B cannot be replicated exactly.
FIG. 8 is a block diagram of a conventional SAD internal clock signal generator circuit 10 for adjusting the delay in a delay monitor by another method and a data input/output circuit 20 for inputting and outputting data in synchronization with the internal clock signal generated at the circuit 10.
To increase the accuracy of the delay in the delay monitor 12B, the delay monitor 12B includes a receiver 12B-1 having almost the same delay as that of the clock receiver 11, a driver 12B-2 having almost the same delay as that of the clock driver 16A, an output control circuit 12B-3 having the same delay as that of the output control circuit 16B, a buffer 12B-4 having almost the same delay as that of the output buffer 22, and a driver 12B-5 having almost the same delay as that of the output driver 23, which are connected in series to construct the delay monitor 12B as a pseudo data input/output route circuit. A capacitance 12B-6 having the value equivalent to the load capacitance 32 of the external data bus 30 is connected to the output of the driver 12B-5.
In the circuit of FIG. 8, however, to cause the delay monitor 12B to replicate the signal delay on the route from the input node to data output node of the external clock signal, circuits each having equivalent circuit configurations to those of all the circuits present on the route must be provided in the delay monitor 12B. Consequently, the circuit area is very large.
The fixed capacitance 12B-6 cannot replicate the external data bus exactly and, when the external load condition has changed, surely contributes to the occurrence of errors.
As described above, the delay monitor used in the conventional clocked delay control circuit has a fixed delay and therefore cannot deal with the variously changing delay time in the input route circuit and that in the output route circuit. Thus, it is very difficult for the delay monitor to set the actual delay time exactly.
When a delay monitor is composed of a pseudo data input/output route circuit to improve the accuracy of synchronization, the circuit area increases. In addition, because the delay is fixed, exact monitoring is impossible. Thus, this contributes to a serious drops in the accuracy of the synchronization of the internal clock signal with the external clock signal in the clocked delay control circuit.
Another problem encountered when a delay monitor is composed of a pseudo data input/output circuit is the current consumption in the circuits. A current-mirror circuit is used in a receiver whose circuit configuration is equivalent to the clock receiver provided as a pseudo data input/output route circuit. Since in the current-mirror circuit, a pass-through current is constantly flowing, this increases the drawn current in a low-power-consumption mode, such as a power-down mode.
Furthermore, because the delay monitor operates each time the data is accessed, the huge-sized transistors provided in the output driver or the like are driven every cycle, which is disadvantageous from the viewpoint of drawn current.